Similar to the mechanical hard disk, solid storage device (SSD) is a large capacity, non-volatile storage device used for computer system. Solid storage device in general uses Flash as storage medium. In Chinese patent documents CN102043689A the solid storage device as shown in FIG. 13 is disclosed. FIG. 13 shows the function block diagram of the general present solid storage devices, including the host system 1301 and solid storage device 1302. Thereinto, the solid storage device 1302 includes the interface module 1303, solid storage processor 1304, as well as Flash array 1306 consisting of Flash chip 1305 as a unit. Among them, the interface module 1303 is mainly used for implementing the interface protocol consistent with the host system, such as SATA (Serial Advanced Technology Attachment), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), SCSI (Small ComputerSystem Interface), IDE (Integrated Drive Electronics) etc. Through the interface module 1303, the solid storage device shows the host system a standard storage device with certain logic space. Solid storage processor 1304 is the control core of the whole storage device, which is mainly in charge of the control signals and data transmission between the interface module 1303 and flash array 1306, Flash management, conversion or mapping from the host logical address to Flash physical address, wear-leveling (the logical addresses are mapped to different physical addresses so as to prevent a single Flash chip from being concentratedly operated and disabled early), bad block management and so on. Solid storage processor 1304 can be implemented by a variety of software, hardware, firmware or their combination. 1305 is the individual Flash chip, and Flash array 1306 is consisting of a plurality of Flash chip 1305.
In order to improve the reading and writing speed of the solid storage device, random access memories such as DRAM or SRAM or other types of high speed reading/writing memories can be set up in the solid storage device, serving as cache memory when reading and writing data from the Flash. In the process of the storage device access, as an example, the computer sends SCSI (small computer system interface) command to the storage device, and the storage device receives and processes the SCSI command, executing corresponding storage medium reading and writing process according to the operation that the SCSI command indicates. In this process, the SCSI command does not directly operate the high speed buffer memory. That means, the cache memory is “transparent” to the computer or user. There are also some storage devices providing cache memory “flushing” mechanism, which means the computer or user can use a predetermined command to force the storage device to write the data in the cache memory to the non-volatile storage medium (for example, a disk or flash memory).
However, allocation and management of the cache memory will become the burden of the controller on the solid storage device. And when the cache memory is fully occupied, if the solid storage device receives new access request from the host system, it also needs to perform replace operations on the cache memory. Thus not only the complexity of the controller is increased, but also the host will experience bump on read/write performance over.
DMA (Direct Memory Access) transmission can also be executed between the host and the device. Method and device for executing DMA transmission is disclosed in the Chinese patent documents CN101221544A. A typical procedure of DMA transmission is Scatter/Gather operation. In the scatter/gather operation, a plurality of data blocks to be transmitted are stored at multiple discontinuous address location in the system (host) memory. The processor does not need to provide programming operation to the DMA controller for each data block being moved from a source to a destination, but just sets up descriptor table or the descriptor linked table in the system memory. Descriptor table or the descriptor linked table comprises a set of descriptors, each of which describes the data block's moving direction, source address, destination address and optional number of bytes transmitted. In the case not including number of bytes transmitted in a descriptor, the agreed length data can be transmitted through the DMA mode.